1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same.
2. Description of the Related Art
Static random access memories (SRAMs) of semiconductor integrated circuit devices have advantages of low power consumption and fast operating speed as compared to dynamic RAMs (DRAMs). The SRAMs are thus widely used in portable appliances or cache memory devices of computers.
Unit cells of SRAM devices are typically classified into two categories. One is a high load resistor SRAM cell employing a high-resistance resistor as a load device, and the other is a complementary metal oxide semiconductor (CMOS) SRAM cell employing a P-channel MOS (PMOS) transistor as a load device.
The CMOS SRAM cell is again classified into two types. One is a thin film transistor (TFT) SRAM cell employing a TFT stacked on a semiconductor substrate as a load device, and the other is a bulk CMOS SRAM cell employing a bulk transistor formed at a semiconductor substrate as a load device.
The bulk CMOS SRAM cell exhibits high cell stability as compared to the TFT SRAM cell and the high resistor SRAM cell. That is, the bulk CMOS SRAM cell has an excellent low operation voltage characteristic and a low stand-by current characteristic. This is because all transistors constituting the bulk CMOS SRAM cell are formed on a single crystalline silicon substrate whereas the TFT is typically fabricated using a polysilicon layer as a body layer. However, the bulk CMOS SRAM cell has low integration density and weak latch-up immunity as compared to the TFT SRAM cell. Accordingly, in order to implement a highly integrated SRAM device having high reliability, it is required to continuously improve the characteristics of the TFTs (load transistors) employed in the TFT SRAM cell.
Semiconductor devices having TFTs stacked on a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766 to Chen et al., entitled “Semiconductor structure incorporating thin film transistors and methods for its manufacture”. According to Chen et al., a bulk transistor is formed at a single crystalline silicon substrate, and a TFT is stacked over the bulk transistor. A body layer of the TFT is fabricated by forming an amorphous silicon layer over the semiconductor substrate having the bulk transistor and then crystallizing the amorphous silicon layer through an annealing process. In this case, the body layer corresponds to a polysilicon layer having large grains. That is, it is difficult to transform the body layer into a perfect single crystalline silicon layer. As a result, it is difficult to form the TFT having the electrical characteristics of the bulk transistor. Accordingly, methods for improving the characteristics of the TFT stacked over the semiconductor substrate are required.